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1 preliminary cat35c704 4k-bit secure access serial e 2 prom features n single 5v supply n password read/write protection: 1 to 8 bytes n memory pointer write protection n sequential read operation n 256 x16 or 512 x 8 selectable serial memory n high speed synchronous protocol n commercial, industrial and automotive temperature ranges n operating frequency: dcC3mhz n low power consumption: Cactive: 3 ma Cstandby: 250 m a n 100,000 program/erase cycles n 100 year data retention pin functions pin name function cs chip select do (1) serial data output clk clock input di (1) serial data input pe parity enable err error indication pin v cc +5v power supply gnd ground note: (1) di, do may be tied together to form a common i/o. description the cat35c704 is a 4k-bit serial e 2 prom that safe- guards stored data from unauthorized access by use of a user selectable (1 to 8 byte) access code and a movable memory pointer. two operating modes provide unprotected and password-protected operation allow- ing the user to configure the device as anything from a rom to a fully protected no-access memory. the cat35c704 uses a unique serial-byte synchronous communication protocol and has a sequential read feature where data can be sequentially clocked out of the memory array. the device is available in 8-pin dip or 16-pin soic packages. 35c704 f02 block diagram 5074 fhd f01 pin configuration soic package (j) dip package (p) cs clk di do v cc pe err gnd di do nc nc err gnd nc nc nc nc cs clk nc nc v cc pe 1 2 3 4 8 7 6 5 1 2 3 4 16 15 14 13 512 611 710 89 ? 1998 by catalyst semiconductor, inc. characteristics subject to change without notice serial communi- cation block instruction register instruction decoder status register 64-bit access code & control block 4k-bit eeprom array r/w buffer address decoder address register memory pointer do clk pe cs di err v cc gnd doc. no. 25045-00 2/98
2 preliminary cat35c704 doc. no. 25045-00 2/98 absolute maximum ratings* temperature under bias ................. C55 c to +125 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to ground (1) ........... C2.0v to +v cc + 2.0v v cc with respect to ground ............... C2.0v to +7.0v package power dissipation capability (t a = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. reliability characteristics symbol parameter min. max. units reference test method n end (3) endurance 100,000 cycles/byte mil-std-883, test method 1033 t dr (3) data retention 100 years mil-std-883, test method 1008 v zap (3) esd susceptability 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 d.c. characteristics v cc = +5v 10%,unless otherwise specified. limits symbol parameter min. typ. max. units test conditions i cc power supply current 3 ma v cc = 5.5v, cs = v cc (operating) do is unloaded. i sb power supply current 250 m av cc = 5.5v, cs = 0v (standby) di = 0v, clk = 0v v il input low voltage C0.1 0.8 v v ih input high voltage 2 v v ol output low voltage 0.4 v i ol = 2.1ma v oh output high voltage 2.4 v i oh = C400 m a i li (5) input leakage current 2 m av in = 5.5v i lo output leakage current 10 m av out = 5.5v, cs = 0v note: (1) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20 ns. m aximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1v to v cc +1v. (5) pe pin test conditions: v ih < v in < v il
preliminary cat35c704 3 doc. no. 25045-00 2/98 note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t hz is measured from the falling edge of the clock to the time when the output is no longer driven. a.c. characteristics v cc = +5v 10%,unless otherwise specified. limits symbol parameter min. typ. max. units test conditions t css cs setup time 150 ns t csh cs hold time 0 ns c l = 100pf t dis di setup time 50 ns v in = v ih or v il t dih di hold time 0 ns v out = v oh or v ol t pd clk to do delay 150 ns t hz (1) (2) clk to do high-z delay 50 ns t ew program/erase pulse width 12 ms t csl cs low pulse width 200 ns t ckh clk high pulse width 165 ns t ckl clk low pulse width 100 ns t sv err output delay 150 ns c l = 100pf t vccs (1) v cc to cs setup time 5 m sc l = 100pf t csz (1) cs to do high-z delay 50 ns t csd cs to do busy delay 150 ns f clk clock frequency dc 3 mhz
4 preliminary cat35c704 doc. no. 25045-00 2/98 password protection the cat35c704 is a 4k-bit e 2 prom that features a password protection scheme to prevent unauthorized access to the information stored in the device. it contains an access code register which stores one to eight bytes of access code along with the length of that access code. additionally, a memory pointer register stores the ad- dress that partitions the memory into protected and unprotected areas. as shipped from the factory, the device is unprogrammed and unprotected. the length of the access code is equal to zero and the memory pointer register points to location zero. every byte of the device is fully accessible without an access code. setting a password and moving the memory pointer register to cover all or part of the memory secures the device. once secured, the memory is divided into a read/write area and a read-only area with the entry of a valid access code. if no access code is entered, the memory is divided into a read-only area and a non-access area. figure 2 illlustrates this partitioning of the memory array. write protection another feature of the cat35c704 is write-protection without the use of an access code. if the memory pointer register is set to cover all or part of the memory, without setting the access code register, the device may be divided into an area which allows full access, and an area which allows read-only access. to write into the read-only area, the user can override the memory pointer register for every write instruction or he can simply move the address in the memory pointer register to uncover this area, and then write into the memory. this mechanism prevents inadvertent overwriting of important data in the memory without the use of an access code. figure 3 illustrates this partitioning of the memory array. 5074 fhd f03 figure 2. secure mode 5074 fhd f04 access register: access code length: memory pointer: pointer register address in memory read-only access password-only access 255 (x16) 511 (x8) 0 access code (1C8 bytes) 1 to 8 aa aa figure 1. a.c. timing v cc cs clk di t vccs do t css t ckh t ckl t csh t hz t dih t dis t pd t pd high-z high-z
preliminary cat35c704 5 doc. no. 25045-00 2/98 read sequential to allow for convenient reading of blocks of contiguous data, the device has a read sequential instruction which accepts a starting address of the block and continuously outputs data of subsequent addresses until the end of memory, or until chip select goes low. the cat35c704 communicates with external devices via a synchronous serial communication protocol (secs) that has a maximum transmission rate of 3 mhz. the data transmission may be a continuous stream of data or it can be packed by pulsing chip select low in between each packet of information. (except for the sequential read instruction where chip select must be held high). pin descriptions cs chip select is a ttl compatible input which, when set high, allows normal operation of the device. any time chip select is set low, it resets the device, terminating all i/o communication, and puts the output in a high impedance state. cs is used to reset the device if an error condition exists or to put the device in a power- down mode to minimize power consumption. it may also be used to frame data transmission in applications where the clock and data input have to be ignored from time to time. although cs resets the device, it does not change the program/erase or the access-enable status, nor does it terminate a programming cycle once it has started. the program/erase and access-enable opera- tions, once enabled, will remain enabled until specific disabling instructions are sent or until power is removed. figure 3. unprotected mode (1) access register: access code length: memory pointer: pointer register address in memory read/write/erase access read-only access 255 (x16) 511 (x8) 0 xx 0 aa aa 5074 fhd f05 figure 4. err pin timing 5074 fhd f06 note: (1) x = dont care; a = address bit. cs clk err t sv t sv high-z
6 preliminary cat35c704 doc. no. 25045-00 2/98 clk the system clock is a ttl compatible input pin that allows operation of the device over a frequency range of dc to 3 mhz. di the data input pin is ttl compatible and accepts data and instructions in a serial format. each instruction must begin with 1 as a start bit. the device will accept as many bytes as an instruction requires, including both data and address bytes. with the secs protocol, extra bits will be disregarded if they are 0s and misinter- preted as the next instruction if they are 1s. an instruc- tion error will cause the device to abort operation and all i/o communication will be terminated until a reset is received. do the data output pin is a tri-state ttl compatible output. it is normally in a high impedance state unless a read or an enable busy instruction is executed. following the completion of a 16-bit or 8-bit data stream, the output will return to the high impedance state. during a pro- gram/erase cycle, if the enable busy instruction has been previously executed, the output will stay low while the device is busy, and it will be set high when the program/erase cycle is completed. do will stay high until the completion of the next instructions op- code and, if the next instruction is a read, do will output the appropriate data at the end of the instruction. if the enable busy instruction has not been previously executed, do will stay in a high impedance state. do will figure 5. program/erase timing 5074 fhd f07 figure 6. cs to do status timing 5074 fhd f08 cs clk di last address bit for erase last opcode bit for eral last data bit for write/wral high-z do t ckh t pd t ew next instruction cs clk di last address bit for erase last opcode bit for eral last data bit for write/wral high-z do t csz next instruction t csd busy ready busy high-z
preliminary cat35c704 7 doc. no. 25045-00 2/98 also go to the high impedance state if an error condition is detected. if the enable busy instruction has not been executed, to determine whether the device is in a program/erase cycle or in an error condition, a read status instruction may be entered. when the device is in a program/erase cycle it will output an 8-bit status word. if it does not, it is in an error condition. pe the parity enable pin is a ttl compatible input. if the pe pin is set high, the device will be configured to commu- nicate using even parity, and if the pin is set low, it will use no parity. in this case, instructions or data that include parity bits will not be interpreted correctly. note: the pe input is internally pulled down to gnd (i.e. default = no parity). as with all cmos devices, cs, clk and di inputs must be connected to either high or low, and not left floating. err the error indication pin is an open drain output. if either an instruction or parity error exists, the err pin will output a 0 until the device is reset. this can be done by pulsing cs low. 5074 fhd f10 figure 8. write timing 5074 fhd f11 figure 7. read timing cs clk di high-z do op 7 a n op 0 a 0 d n d 0 t pd t hz op code address v cc data cs clk di do op 7 a n op 0 a 0 t sv op code address d n d 0 dont care data t ew busy ready
8 preliminary cat35c704 doc. no. 25045-00 2/98 device operation instructions the cat35c704 instruction set includes 19 instruc- tions. six instructions are related to security or write protec- tion: disac disable access enac enable access macc modify access code ovmpr override memory pointer register rmpr read memory pointer register wmpr write memory pointer register six instructions are read/write/erase instructions: eral clear all locations erase clear memory locations read read memory rseq read sequentially wral write all write write memory note: all write instructions will automatically perform a clear before writing data. seven instructions are used as control and status func- tions: disbsy disable busy enbsy enable busy ewen program/erase enable ewds program/erase disable nop no operations org select memory organization rsr read status register unprotected mode as shipped from the factory, the cat35c704 is in the unprotected mode. the access code length is set to 0, and the memory pointer is at address 00 hex. while in this mode, any portion of the e 2 prom array can be read or written to without an access code. a portion of the memory may be protected from any write or clear operation by setting the memory pointer to the appropri- ate address via the wmpr (write memory pointer register) instruction: wmpr [address] 5074 fhd f13 cs clk di high-z do op 7 a n op 0 a 0 t sv t ew op code address dont care busy ready figure 10. erase timing 5074 fhd f12 cs clk di high-z do op 7 op 0 op code figure 9. ewen/ewds timing
preliminary cat35c704 9 doc. no. 25045-00 2/98 as shown previously in figure 3, memory locations below the address set in the memory pointer will be program/erase protected. thus, unintentional clearing or writing of data in this area will be prevented, while memory locations at or above the protected area still allow full access. this protection does not apply to the eral and wral commands which are not blocked by the memory pointer. secure mode as shown previously in figure 2, in the secure mode, memory locations at or above the address set in the memory pointer allow read-only access. memory loca- tions below that address will require an access code before they can be accessed. the secure mode is activated with an macc (modify access code) instruc- tion followed by a user access code which can be one to eight bytes in length. ewen macc [old code][new code][new code] the ewen instruction enables the device to perform program/erase operations. the new access code must be entered twice for verification. if the device already has an access code, the old access code must be entered before the new access code can be accepted. the length of the password is incorporated into the macc portion of the instruction. once the secure mode is activated, access to memory locations is under software control. access (read, write, and clear instructions) to the memory locations below the address in the memory pointer is allowed only if the enac (enable access) instruction followed by the cor- rect access code has been previously executed. enac [access code] ewen write [address][data] the enac instruction, along with the access code, enables access to the protected area of the device. the ewen instruction enables execution of the program/ erase operations. this portion of the memory is other- wise inaccessible for any operation. read-only access is allowed without the access code for memory locations at or above the address in the memory pointer. the access code can be changed by the following instruction: enac [old access code] ewen macc [old code][new code][new code] a two-tier protection scheme is implemented to protect data against inadvertent clearing or writing. to write to the memory, an ewen (program/erase enable) must first be issued. the cat35c704 will now allow program/ erase operations to be performed only on memory locations at or above the address set in the memory pointer. the remaining portion of the memory is still protected. to override this protection, an ovmpr (over- ride memory pointer registersee memory pointer register) must be issued for every program/erase in- struction which accesses the protected area: enac [access code] ewen ovmpr write [address][ data] as an alternative to the ovmpr instruction, the wmpr (write memory pointer register) instruction may be used to move the memory pointer address to uncover the area where writing is to be performed: enac [access code] ewen wmpr [address] write [address ][data ] figure 11. eral timing 5074 fhd f14 cs clk di do op code op code op 7 op 0 op 0 op 7 t sv t ew high-z dont care busy ready
10 preliminary cat35c704 doc. no. 25045-00 2/98 as shipped from the factory, the device is in the unpro- tected mode. the length of the access code is user selectable from a minimum of one byte to a maximum of eight bytes (> 1.84x10 19 combinations). loading a zero- length access code will disable protection. memory pointer register the memory pointer enables the user to segment the e 2 prom array into two sections. in the unprotected mode, the array can be segmented between read-only and full access, while in the secure mode, the memory may be segmented between read-only access and password-only access. three instructions are dedicated to the memory pointer operations. the first one is wmpr (write memory pointer register). this instruction, fol- lowed by an address, will load the memory pointer register with a new address. this address will be stored in the e 2 prom and can be modified only by another wmpr instruction. the second instruction is ovmpr (override memory pointer register) which allows a single program/erase to be performed to memory loca- tions below the address set in the memory pointer. this instruction allows the user to modify data in a segmented array without having to move the memory pointer. once the operation is complete, the device returns to the protected mode. if the device is in the secure mode both of these instructions require the enac instruction and a valid access code prior to their execution. the third instruction is the rmpr (read memory pointer regis- ter) which will place the current contents of the register in the serial output buffer. secs protocol the cat35c704 implements the secs communication protocol which uses an 8-bit transmission format. as shown in figures 7C13, all instructions are 8 bits long with the first bit being the start bit and the following 7 bits being the op-code. data can be one or two bytes long depending on the instruction and the memory array organization. each address is one or two bytes long depending on the organization of the memory array. in this protocol, the transmission of the msb is always first and the lsb last. the cs (chip select) pin of the cat35c704 may be used to frame the data transmis- sion packet or it may be set high for the entire duration of operation. if an error in op-code or parity (if enabled) has been detected, the err output will be set low and the cat35c704 will stop receiving and sending data until cs is toggled from high to low to high again. alternatively, an error condition may be detected by interrogating the device for a status word. if an error condition has been detected, the do (data output) pin will not respond. do may be programmed to become tri- stated or to output a rdy/busy status flag during program/erase cycles (see enbsy instruction). status register an eight bit status register is provided to allow the user to determine the status of the cat35c704. the contents of the first three bits of the register are 101 which allows the user to quickly determine the condition of the device. the next three bits indicate the status of the device; they are parity error, instruction error and rdy/busy status. the last two bits are reserved for future use. clear all and write all as a precaution, the eral instruction has to be entered twice before it is executed. this measure is required as a redundancy check on the incoming instruction for possible transmission errors. the wral instruction requires sending an eral first (this sets a flag only) and then the wral instruction. the cat35c704 will accept figure 12. wral timing 5074 fhd f15 cs clk di do op code eral op code wral op 7 op 0 op 0 op 7 t sv t ew high-z dont care data busy ready
preliminary cat35c704 11 doc. no. 25045-00 2/98 the following commands: eral eral an eral will be executed eral wral a wral will be executed both the eral and wral commands will program/ erase the entire array and will not be blocked by the memory pointer. the parity bit the secs protocol supports an even parity bit if the pe pin of the device is set high, otherwise, there is no parity. if pe is set low and the incoming instruction contains a parity bit, it may be interpreted as the start bit of the next instruction. when pe is high, the cat35c704 expects a parity bit at the end of every incoming instruc- tion packet. for example, the rseq instruction will look like this: 1100 1011 a15a8 a7a0 p the device then outputs data continuously until it reaches the end of the memory. the last byte of data contains 9 bits. the ninth bit is the parity bit calculated over the entire transmitted data packet. the rseq instruction may be terminated at any time by bringing cs low; the output will then go to high impedance. system errors whenever an error occurs, be it an instruction error (unknown instruction), or parity error (perhaps caused by transmission error), the device will stop its operation. to return to normal operation, the device must be reset by pulsing cs low and then set back to high. reset- ting the device will not affect the enac, ewen and enbsy status. the error may be determined by entering the read status register (rsr) instruction immediatly following the reset. the status output is an 8 bit word with the first three bits being 101. this three bit pattern indicates that the device is functioning normally. the fourth bit is 1 if a parity error occurred. the fifth bit is a 1 if an instruction error occurred. the sixth bit is a 1 if the device is in a program/erase cycle. the last two bits are reserved for future use. the reason for the 101 pattern is to distinguish be- tween an error conditon (do tri-stated) and a device busy status. if an error condition exists, it will not respond to any input instruction from di. however, if the device is in a program/erase cycle, it responds to the rsr instruc- tion by outputting 101 00100. if rsr is executed at the end of a program/erase cycle, the output will be 101000 00. 5074 fhd f09 figure 13. next instruction timing (1) 5074 fhd f16 note: (1) do will be high impedance after the last instruction bit has been clocked in, unless the instruction is rsr or rmpr, in whic h case, do will become active. parity error instruction error rdy/busy status future use 1 0 1 x x x x x cs clk di do op code next instruction high-z t hz t ew t sv ready busy high-z
12 preliminary cat35c704 doc. no. 25045-00 2/98 instruction set disac disable access 1000 1000 this instruction will lock the memory from all program/ erase operations regardless of the contents of the memory pointer. a write can be accomplished only by first enter- ing the enac instruction followed by a valid access code. enac enable access 1100 0101 [access code] in the protected mode, this instruction, followed by a valid access code, unlocks the device for read/write/ clear access. wmpr write memory pointer register 1100 0100 [a15Ca8] [a7Ca0] (x8 organization) [a7Ca0] (x16 organization) 1100 0100 the wmpr instruction followed by 8 or 16 bits of address (depending on the organization) will move the pointer to the newly specified address. macc modify access code 1101 [length] [old code] [new code] [new code] this instruction requires the user to enter the old access code, if one was set previously, followed by the new access code and a re-entry of the new access code for verification. within the instruction format, the variable [length] designates the length of the access code as the following: [length] = [0] no access code. set device to unpro- tected mode. [length] = [1C8] length of access code is 1 to 8 bytes. [length] = [>8] illegal number of bytes. the cat35c704 will ignore the rest of the transmission. rmpr read memory pointer register 1100 1010 output the content of the memory pointer register to the serial output port. ovmpr override memory pointer register 1000 0011 override the memory protection for the next instruction. read read memory 1100 [a7Ca0] (x16 organization) 1100 1001 1001 [a15Ca8] [a7Ca0] (x8 organization) output the contents of the addressed memory location to the serial port. write write memory 1100 [a7Ca0] [d15Cd8] [d7Cd0] (x16 organization) 1100 0001 0001 [a15Ca8] [a7Ca0] [d7Cd0] (x8 organization) write the 8 bit or 16 bit data to the addressed memory location. after the instruction, address, and data have been entered, the self-timed program/erase cycle will start. the addressed memory location will be erased before data is written. the do pin may be used to output the rdy/busy status by having previously entered the enbsy instruction. during the program/erase cycle, do will output a low for busy during this cycle and a high for ready after the cycle has been completed. erase clear memory 1100 [a7Ca0] (x16 organization) 1100 0000 0000 [a15Ca8] [a7Ca0] (x8 organization) erase data in the specified memory location (set memory to 1). after the instruction and the address have been entered, the self-timed clear cycle will start. the do pin may be used to output the rdy/busy status by having previously entered the ensby instruction. during the clear cycle, do will output a low for busy during this cycle and a high for ready after the cycle has been completed. eral clear all 1000 1000 1001 1001 erase the data of all memory locations (all cells set to 1). for protection against inadvertent chip clear, the eral instruction is required to be entered twice. wral write all 1000 1100 0011 1001 [d15Cd8] [d7Cd0] (x16 organization) 1000 1100 0011 1001 [d7Cd0] (x8 organization) write one or two bytes of data to all memory locations. an eral will be automatically performed before the
preliminary cat35c704 13 doc. no. 25045-00 2/98 wral is executed. for protection against inadvertent clearing or writing of data, the eral instruction is required to be entered preceding the wral instruction. rseq read sequentially 1100 1100 1011 1011 [a7Ca0] (x16 organization) [a15Ca8] [a7Ca0] (x8 organization) read memory starting from specified address, sequen- tially to the highest address or until cs goes low. the instruction is terminated when cs goes low. enbsy enable busy 1000 0100 enable the status indicator on do during program/erase cycle. do goes low then high once the write cycle is complete. do will go to high-z at the end of the next op code transmission. disbsy disable busy 1000 0101 disable the status indicator on do during program/ erase cycle. ewen program/erase enable 1000 0001 enable program/erase to be performed on non-pro- tected portion of memory. this instruction must be entered before any program/erase instruction will be carried out. once entered, it will remain valid until power- down or an ewds (program/erase disable) is ex- ecuted. ewds program/erase disable 1000 0010 disable all write and clear functions. org select memory organization 1000 011r (where r = 0 or 1) set memory organization to 512 x 8 if r = 0. set memory organization to 256 x 16 if r = 1. rsr read status register 1100 1000 output the contents of the 8-bit status register. the contents of the first three bits of the register are 101, which allows the user to quickly determine whether the device is listening or is in an error condition. the next three bits indicate parity error, instruction error and rdy/ busy status. the last two bits are reserved for future use. nop no operation 1000 0000 no operation. ordering information notes: (1) the device used in the above example is a 35c704ji-te13 (soic, industrial temperature, tape & reel) 35c704 f17 prefix device # suffix 35c704 j i -te13 product number tape & reel te13: 2000/reel package p: pdip j: soic (jedec) cat temperature range blank = commercial (0?c to +70?c) i = industrial (-40?c to +85?c) a = automotive (-40? to +105?c)* * -40?c to +125?c is available upon request optional company id
14 preliminary cat35c704 doc. no. 25045-00 2/98

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